M_ACTIVITY=Val_0x0, M_RX_OVER=Val_0x0, M_RX_FULL=Val_0x0, M_TX_OVER=Val_0x0, M_SCL_STUCK_AT_LOW=Val_0x0, M_MASTER_ON_HOLD_READ_ONLY=Val_0x0, M_RD_REQ=Val_0x0, M_RX_UNDER=Val_0x0, M_RX_DONE=Val_0x0, M_GEN_CALL=Val_0x0, M_TX_EMPTY=Val_0x0, M_START_DET=Val_0x0, M_RESTART_DET_READ_ONLY=Val_0x0, M_STOP_DET=Val_0x0, M_TX_ABRT=Val_0x0
Interrupt Mask Register
| M_RX_UNDER | This bit masks the R_RX_UNDER interrupt in I2C_INTR_STAT register. 0 (Val_0x0): RX_UNDER interrupt is masked 1 (Val_0x1): RX_UNDER interrupt is unmasked |
| M_RX_OVER | This bit masks the R_RX_OVER interrupt in I2C_INTR_STAT register. 0 (Val_0x0): RX_OVER interrupt is masked 1 (Val_0x1): RX_OVER interrupt is unmasked |
| M_RX_FULL | This bit masks the R_RX_FULL interrupt in I2C_INTR_STAT register. 0 (Val_0x0): RX_FULL interrupt is masked 1 (Val_0x1): RX_FULL interrupt is unmasked |
| M_TX_OVER | This bit masks the R_TX_OVER interrupt in I2C_INTR_STAT register. 0 (Val_0x0): TX_OVER interrupt is masked 1 (Val_0x1): TX_OVER interrupt is unmasked |
| M_TX_EMPTY | This bit masks the R_TX_EMPTY interrupt in I2C_INTR_STAT register. 0 (Val_0x0): TX_EMPTY interrupt is masked 1 (Val_0x1): TX_EMPTY interrupt is unmasked |
| M_RD_REQ | This bit masks the R_RD_REQ interrupt in I2C_INTR_STAT register. 0 (Val_0x0): RD_REQ interrupt is masked 1 (Val_0x1): RD_REQ interrupt is unmasked |
| M_TX_ABRT | This bit masks the R_TX_ABRT interrupt in I2C_INTR_STAT register. 0 (Val_0x0): TX_ABORT interrupt is masked 1 (Val_0x1): TX_ABORT interrupt is unmasked |
| M_RX_DONE | This bit masks the R_RX_DONE interrupt in I2C_INTR_STAT register. 0 (Val_0x0): RX_DONE interrupt is masked 1 (Val_0x1): RX_DONE interrupt is unmasked |
| M_ACTIVITY | This bit masks the R_ACTIVITY interrupt in I2C_INTR_STAT register. 0 (Val_0x0): ACTIVITY interrupt is masked 1 (Val_0x1): ACTIVITY interrupt is unmasked |
| M_STOP_DET | This bit masks the R_STOP_DET interrupt in I2C_INTR_STAT register. 0 (Val_0x0): STOP_DET interrupt is masked 1 (Val_0x1): STOP_DET interrupt is unmasked |
| M_START_DET | This bit masks the R_START_DET interrupt in I2C_INTR_STAT register. 0 (Val_0x0): START_DET interrupt is masked 1 (Val_0x1): START_DET interrupt is unmasked |
| M_GEN_CALL | This bit masks the R_GEN_CALL interrupt in I2C_INTR_STAT register. 0 (Val_0x0): GEN_CALL interrupt is masked 1 (Val_0x1): GEN_CALL interrupt is unmasked |
| M_RESTART_DET_READ_ONLY | This bit masks the M_RESTART_DET_READ_ONLY interrupt in I2C_INTR_STAT register. 0 (Val_0x0): RESTART_DET interrupt is masked 1 (Val_0x1): RESTART_DET interrupt is unmasked |
| M_MASTER_ON_HOLD_READ_ONLY | This bit masks the M_MASTER_ON_HOLD_READ_ONLY interrupt in I2C_INTR_STAT register. 0 (Val_0x0): MASTER_ON_HOLD interrupt is masked 1 (Val_0x1): MASTER_ON_HOLD interrupt is unmasked |
| M_SCL_STUCK_AT_LOW | This bit masks the R_SCL_STUCK_AT_LOW interrupt in I2C_INTR_STAT register. 0 (Val_0x0): SCL_STUCK_AT_LOW interrupt is masked 1 (Val_0x1): SCL_STUCK_AT_LOW interrupt is unmasked |